1. Field of the Invention
The present invention is a clock bus system for use on very large-scale integrated (VLSI) circuits.
2. Description of the Prior Art
Modern digital computers are formed by hundreds of thousands and even millions of logic elements. In computer architectures which are highly integrated, these logic elements are fabricated on very large-scale integrated (VLSI) circuit chips known as gate arrays. The gate arrays themselves are organized onto a plurality of major function circuit boards which are dedicated to the performance of specific tasks. A supercomputer, for example, can include a central processing unit (CPU), memory interface, and input/output (I/O) major function circuit boards. Each of these circuit boards will typically be formed by hundreds of gate arrays.
In order to achieve a high data throughput, operations are distributed throughout the computer and performed in "parallel." Processed data and microinstructions are communicated between individual gate arrays and between major function circuit boards. It is extremely important, therefore, that all microinstructions and data transfers executed by the gate arrays be synchronized with those of other gate arrays. To this end, the computer includes a central clock distribution system for providing a clock signal in the form of a synchronized train of clock pulses to all gate arrays. A clock system of this type is disclosed in an application entitled "Electronic Clock Tuning System", Ser. No. 06/814,654, filed Dec. 30, 1985, and assigned to the same assignee as the present invention.
Once the clock signal is received from the central clock distribution system, a clock bus system on each gate array distributes the clock signal to each individual circuit element. For the very same reasons that each gate array must receive synchronized clock signals from the central clock distribution system, it is imperative that each circuit element on the gate array receive a synchronized train of clock pulses from the clock bus system.
Even minute discrepancies between the phases of clock pulse trains arriving at different circuit elements on a gate array can have disastrous consequences on computer operation. These discrepancies, or skews, are the product of numerous factors. Possibly the most significant factor contributing to skews introduced by the clock bus system are differing conductor path lengths between the terminal on the gate array at which the clock signal is received from the clock distribution system, and the individual circuit elements. Other factors such as operating temperature, supply voltage, component tolerance, and variables due to manufacturing processes also contribute to skew between the clock pulse trains.
The higher the frequency of the clock pulse train, the faster the computer can process data. Frequency of the clock pulse train, however, is limited by the uncertainty, or maximum skew, introduced between clock pulse trains supplied to various circuit elements on the gate array. Simply put, computer performance can be greatly increased by reducing skews introduced by the clock bus system.
Presently, little attention is paid to reducing the skews introduced by clock bus systems. One reason for this lack of attention is the fact that commonly used integrated circuits are relatively small, with the physical distance between the terminal on the circuit at which the clock signal is received, and all circuit elements thereon which require the clock signal, is relatively short. Small differences in length between the conductors therefor introduce little skew.
In one common clock bus system, the clock signal is branched out to all circuit elements on the gate array through a tree-type network formed by a plurality of buffers. The network is made large enough to provide a clock signal to each circuit element which requires it. Still another prior art clock bus structure includes a clock bus which circumscribes all circuit elements on the gate array. Although this clock bus structure permits shorter interconnections between the clock bus and individual circuit elements, delays are introduced by the clock bus itself.
It is evident that there is a continuing need for improved clock bus structures for VLSI circuits. As the size of these circuits continues to increase, the distance between the terminal on the integrated circuit at which the train of clock pulses is received, and each of the circuit elements, can vary widely enough to introduce skews which detract from computer performance. The clock bus system must be capable of providing synchronized trains of clock pulses to all circuit elements on the integrated circuit.